The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. Reduction in the size of MOSFETs has provided continued improvement in speed performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, however, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel.
Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-50 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet when conventional device structures based on bulk silicon (Si) substrates are employed.
For device scaling well into the sub-30-nm regime, a promising approach to controlling short-channel effects is to use an alternative transistor structure with more than one gate, i.e. a multiple-gate transistor. Prior art multiple-gate transistors are formed on silicon-on-insulator substrates. A prior art multiple-gate transistor 10 is shown in plan view in FIG. 1. The structure includes a silicon fin 12 overlying an insulator layer 14, which overlies a substrate (see element 22 in FIG. 2). A gate dielectric (see element 20 in FIG. 2) covers a portion of the silicon fin 12, and a gate electrode 16 straddles across the silicon fin 12. The gate dielectric 20 isolates the gate electrode 16 from the silicon fin 12.
Examples of the multiple-gate transistor include the double-gate transistor, triple-gate transistor, omega field-effect transistor (FET), and the surround-gate or wrap-around gate transistor. A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps suppress short channel effects, and prolongs the scalability of the MOS transistor.
The simplest example of a multiple-gate transistor is the double-gate transistor as described in U.S. Pat. No. 6,413,802 issued to Hu et al. As illustrated in the cross-sectional view of FIG. 2a, the double-gate transistor has a gate electrode 16 that straddles across the channel or the fin-like silicon body 12, thus forming a double-gate structure. There are two gates, one on each sidewall 18 of the silicon fin 12. The plan view of the double-gate structure is shown in FIG. 1.
In U.S. Pat. No. 6,413,802, the transistor channel comprises a thin silicon fin 12 defined using an etchant mask 24 and formed on an insulator layer 14, e.g. silicon oxide. Gate oxidation is performed, followed by gate deposition and gate patterning to form a double-gate structure overlying the sides of the fin. Both the source-to-drain direction and the gate-to-gate direction are in the plane of the substrate surface.
Another example of the multiple-gate transistor is the triple-gate transistor. A cross-sectional view of a triple-gate transistor structure is provided in FIG. 2b. The plan view of the triple-gate structure is shown in FIG. 1. The triple-gate transistor structure has a gate electrode 16 that forms three gates: one gate on the top surface 26 of the silicon body/fin 12, and two gates on the sidewalls 18 of the silicon body/fin 12. The triple-gate transistor achieves better gate control than the double-gate transistor because of it has one more gate on the top of the silicon fin.
The triple-gate transistor structure may be modified for improved gate control, as illustrated in FIG. 2c. Such a structure is also known as the Omega (Ω) field-effect transistor (FET), or simply omega-FET, since the gate electrode 16 has an omega-shape in its cross-sectional view. The encroachment of the gate electrode 16 under the semiconductor fin or body 12 forms an omega-shaped gate structure. It closely resembles the Gate-All-Around (GAA) transistor for excellent scalability, and uses a very manufacturable process similar to that of the double-gate or triple-gate transistor.
The omega-FET has a top gate (adjacent surface 26), two sidewall gates (adjacent surfaces 18), and special gate extensions or encroachments 28 under the fin-like semiconductor body 12. The omega-FET is therefore a field effect transistor with a gate that almost wraps around the body. In fact, the longer the gate extension, i.e., the greater the extent of the encroachment E, the more the structure approaches or resembles the gate-all-around structure. The encroachment of the gate electrode 16 under the silicon body helps to shield the channel from electric field lines from the drain and improves gate-to-channel controllability, thus alleviating the drain-induced barrier lowering effect and improving short-channel performance.